Indian Journal of Science and Technology

Open Access Open Access  Restricted Access Subscription Access

FPGA Based Design of Reed Solomon Codes


Affiliations
1 ECE, Amity School of Engg.& Technol. Bijwasan, New Delhi-110 061, India
2 Thapar University, Patiala, India
 

This paper presents a novel architecture design for forward error correction technique based on RS coding scheme for wireless applications. The design was created using System Generator for DSP tool from Xilinx and was simulated on Matlab/Simulink environment. The hardware description language source code for different blocks was generated and the design was subjected to severe functional and timing constraints using Xilinx Foundation series and ModelSim tools. Synplify Pro tool was finally used to synthesize the complete design. The overall architecture for RS Coder-Decoder was implemented on Xilinx Virtex-II XC2v250 device and consumed slices 1429 for the CODEC at a clock frequency of 90 MHz. The architecture design power consumption analysis was done using the Xilinx Xpower tool and it came out to be about 783 mW.

Keywords

FPGA, Reed-Solomon Coding
User

  • Martyn Riley and Iain Richardson ”An introduction to Reed-Solomon codes: principles, architecture and implementation “ IEEE Conference Proceedings, pp-122-126, New York,1998

  • E. R. Berlekamp ‘Algebric coding theory” McHill New york 1968

  • Barnaad & Saklar “Dgital communication” 2001

  • Azaleah Amina P. Chio, Jonathan A. Sahagun, and Delfin Jay M. Sabido IX “VLSI implementation of a (255, 223) Reed-Solomonerror-correction codec “,SPIE Conference Proceeedings, pp. 256-261, Toronto, 2003

  • Christian SchulerGMD FOKUS Kaiserin-“Code generation tools for hardware implementation of FECcircuits” Berlin, Germany IEEE journal published, vol 22, pp. 1233-1241, August , 1989

  • Arshad Ahmed, Naresh R. Shanbhag, and Ralf Koetter “Systolic interpolation architectures for soft-decodingreed-solomon codes” IEEE journal vol 32, no4, pp. 541-547, 2004.

  • Tong Zhang and Keshab K. Parhi Reed “On the High-Speed VLSI Implementation of Errors-and- Erasures Correcting Reed-Solomon Decoders” IEEE journal of Communications, vol 40, pp 666- 670, August 2005.

  • Tong Zhang and Keshab K. Parhi, IEEE Conference Proceedings, pp. 554-555, 1998, U.SA

  • Sanjay Sharma, Sanjay Attri, R, C, Chauhan, “Low-Power VLSI Synthesis of DSP Systems”, Published in Elsevier Science B. V. INTEGRATION, the VLSI Journal, Issue 1-2, vol. 36, pp. 41-54, September 2003.

  • E. R Berlekamp , “Algebric coding theory” Mcgraw hill , NY 1968

  • E. R Berlekamp, “key papers in the development of coding theory” IEEE proceedigns, pp. 116-119, New York, 1994

  • R. E . Blahut theory and practice of error control codes . Addison-Wesley, MA , 1983


Abstract Views: 390

PDF Views: 83




  • FPGA Based Design of Reed Solomon Codes

Abstract Views: 390  |  PDF Views: 83

Authors

Shivani Pasricha
ECE, Amity School of Engg.& Technol. Bijwasan, New Delhi-110 061, India
Sanjay Sharma
Thapar University, Patiala, India

Abstract


This paper presents a novel architecture design for forward error correction technique based on RS coding scheme for wireless applications. The design was created using System Generator for DSP tool from Xilinx and was simulated on Matlab/Simulink environment. The hardware description language source code for different blocks was generated and the design was subjected to severe functional and timing constraints using Xilinx Foundation series and ModelSim tools. Synplify Pro tool was finally used to synthesize the complete design. The overall architecture for RS Coder-Decoder was implemented on Xilinx Virtex-II XC2v250 device and consumed slices 1429 for the CODEC at a clock frequency of 90 MHz. The architecture design power consumption analysis was done using the Xilinx Xpower tool and it came out to be about 783 mW.

Keywords


FPGA, Reed-Solomon Coding

References





DOI: https://doi.org/10.17485/ijst%2F2009%2Fv2i4%2F29431