Internal Dynamic Partial Reconfiguration for Real Time Signal Processing on FPGA

Few FPGAs support creation of partially reconfigurable systems when compared to traditional systems based on total reconfiguration. This allows dynamic change of the functionalities hosted on the device when needed and while the rest of the system continues its working. Runtime partial reconfiguration of FPGA is an attractive feature which offers countless benefits across multiple industries. Xilinx has supported partial reconfiguration for many generations of devices. This can be taken advantage of substituting inactive parts of hardware systems and to adapt the complete chip a different requirement of an application. This paper describes an innovative implementation for real time audio and video processing using run time internal partial reconfiguration. System is implemented on Virtex-4 FPGA. Internal reconfiguration is handled using internal configuration access port (ICAP) driven by soft processor core. The considerable savings in device resources, bit stream size and configuration time is observed and tabulated in this paper.