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FPGA implementation of improved version of the Vigenere cipher


Affiliations
1 Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran, Islamic Republic of
2 Faculty of Engineering, Islamic Azad University-Tabriz Branch, Tabriz, Iran, Islamic Republic of
3 Faculty of Mathematical Sciences, University of Tabriz, Tabriz, Iran, Islamic Republic of
 

The use of cryptography has become increasingly important in recent years. Currently there are several good methods for encryption like AES and DES. Both of these algorithms require several rounds to encrypt a relatively small block of data. Stream ciphers, like Vigenere and Caesar in particular, only require one round. The Vigenere and Caesar ciphers, however, can be easily broken. Improved version of the Vigenere algorithm is obtained by adding random bits of padding to each byte to diffuse the language characteristics and this make the cipher unbreakable. In this paper we will present an efficient method for hardware implementation of the improved Vigenere algorithm.

Keywords

Cryptography, Vigenere Algorithm, FPGA
User

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  • FPGA implementation of improved version of the Vigenere cipher

Abstract Views: 384  |  PDF Views: 103

Authors

Massoud Sokouti
Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran, Islamic Republic of
Babak Sokouti
Faculty of Engineering, Islamic Azad University-Tabriz Branch, Tabriz, Iran, Islamic Republic of
Saeid Pashazadeh
Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran, Islamic Republic of
Leili Mohammad Khanli
Faculty of Mathematical Sciences, University of Tabriz, Tabriz, Iran, Islamic Republic of

Abstract


The use of cryptography has become increasingly important in recent years. Currently there are several good methods for encryption like AES and DES. Both of these algorithms require several rounds to encrypt a relatively small block of data. Stream ciphers, like Vigenere and Caesar in particular, only require one round. The Vigenere and Caesar ciphers, however, can be easily broken. Improved version of the Vigenere algorithm is obtained by adding random bits of padding to each byte to diffuse the language characteristics and this make the cipher unbreakable. In this paper we will present an efficient method for hardware implementation of the improved Vigenere algorithm.

Keywords


Cryptography, Vigenere Algorithm, FPGA

References





DOI: https://doi.org/10.17485/ijst%2F2010%2Fv3i4%2F29736