A Novel 8 Bit Digital Comparator for 3x3 Fixed Kernel Based Modified Shear Sorting

The need for an optimized area, speed and power plays a vital role for any median filter is good at removing impulse noise without degrading the image details. The main operation of the median is Rank ordering. It is a computationally complex operation, so it is hard to implement it in real time. This paper introduces a new sorting technique called for Snake like sorting. The proposed Sorting technique is implemented as a parallel architecture. This algorithm is a Mesh based sorting that require less number of comparators for rank ordering. The proposed architecture is compared with other Rank Ordering algorithm on the basis of power, speed, and area and found to exhibit good results. The proposed architecture is implemented on parallel and pipelined schemes and is targeted for Spartan 3e Device with gate capacity 5000 using Xilinx 7.1i compiler version. The pipelined scheme has an operating frequency of 81 Mhz occupying 283 slices with a gate count of 5,640.