Booth Multiplier Using Reversible Logic with Low Power and Reduced Logical Complexity

The proposed testable reversible architecture scheme yields significantly reduced complexity, low power and high speed features. It is a key issue in the interface of computation and physics, and of growing importance as miniaturization progresses towards its physical limits. With the advent of nanotechnology the fault detection and testability is of high interest for accuracy. This research work describes the reversible testable design of high-speed modified Booth multipliers. The proposed multiplier circuits are based on the modified Booth algorithm can be used to accelerate the multiplication speed with reduced power consumption. The resultant multiplier circuit shows better performance than others and can be used in the systems requiring very high performance. The proposed booth multiplier design shows 12% reduced logical complexity, 10% reduced power consumption and efficient device utilization achieved in comparison to existing reversible logic.