Robust Logic Circuits Design Using SOI Shorted-Gate FinFETs

The scaling of planar Metal Oxide Semiconductor Field Effect Transistor (MOSFET) technology has reached to its extremity. Double Gate (DG) device was introduced to derive the benefits of scaling gate lengths. Fin-shaped Field Effect Transistors (FinFETs) proved to be the best architecture to realize a double gate structure. In this paper, a static leakage control technique is proposed and a ring-oscillator of five inverters based on shorted gate (SG) FinFETs is simulated using the technique. The basic logic gates like Inverter, 2-input NAND gate, and 2-input NOR gate are simulated using the proposed technique. Leakage power and Power Delay Product (PDP) optimization of 93.46% and 97.78% has been found in 2-input SG FinFET-based proposed NAND gate compared to that of 2-input SG FinFET-based conventional NAND gate. Also, SG FinFET-based proposed 2-input NOR gate shows 98.03% and 98% optimization of leakage power and PDP, respectively compared to the SG FinFET-based conventional 2-input NOR gate. The proposed SG FinFET-based ring-oscillator shows a leakage power and PDP optimization of 62.12% and 35.56%, respectively in comparison to the conventional SG FinFET-based ring-oscillator. The reliability of the proposed circuit is calculated, which came out to be the highest at 0.7V supply and 16nm process node for a 10% deviation in operating parameters. Also, the process parameter variation of leakage power, delay, and PDP of the proposed circuit came out to be proper and stable thus maintaining the functionality of the proposed circuit.