Open Access
Subscription Access
Open Access
Subscription Access
A 30nW Sub-Threshold Adiabatic Carry Look-Ahead Adder in 90nm CMOS
Subscribe/Renew Journal
A sub-threshold adiabatic operation is one of the popular solutions to achieve ultra low power in the realization of modern digital circuits. The proposal of this paper is to design a 4-bit Sub-threshold Adiabatic- Carry Look-Ahead adder (SA-CLA) by utilizing the leakage current as the switching current and the energy stored in the capacitor is recycled instead of discharging it. The proposed SA-CLA has been designed and implemented in 90nm CMOS. The circuit is simulated at different combinations of source voltages and frequencies. The circuit yields a power consumption of 30nW with 400mV supply at 100 KHz.
Keywords
Sub-Threshold Adiabatic-Carry Look-Ahead Adder SA-CLA, Ultra Low Power Consumption, SA-PMOS, SA-NMOS, CADENCE.
User
Subscription
Login to verify subscription
Font Size
Information
- Manash Chanda, Sankalp Jain,Swapnadip De, and Chandan Kumar Sarkar, “Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Applications” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 12, pp: 2782 – 2790, Dec. 2015.
- H. Soeleman, K. Roy, and B. C. Paul, “Robust subthreshold logic for ultra-low power operation,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 1, pp. 90–99, Feb. 2001.
- Yong Moon, Deog-Kyoon Jeong, “An Efficient Charge Recovery Logic Circuit” IEEE Journal of Solid-State Circuits. vol. 31. no.4. april. 1996
- C.-S. A. Gong, M.-T. Shiue, C.-T. Hong, and K.-W. Yao, “Analysis and design of an efficient irreversible energy recovery logic in 0.18-μm CMOS,” IEEE Transactions on Circuits and Systems I, Vol. 55, no. 9, pp: 2595 – 2607, Oct. 2008.
- M.V.S. Chaitanya kumar, J. Selva kumar, “Dual Mode Logic Carry Look Ahead Adder” IEEE International Conference on Advanced Communication Control and Computing Technologie, may. 2014.
- Dragan Maksimovic ́, Vojin G. Oklobdžija, Borivoje Nikolic ́, and K. Wayne Current “Clocked CMOS Adiabatic Logic with Integrated Single.
- Manish Mittal And C. Andre T. Salama “DPTL 4-B Carry Lookahead Adder” IEEE Journal of Solid-State Circuits, Volume: 27, Issue: 11, pp: 1644-1647, Nov. 1992
- Priya Gupta, Ishan Munje, Nikhil Kaswan “Analysis & Implementation of Ultra Low-Power 4-bit CLA in Subthreshold Regime” International Conference on Circuit, Power and Computing Technologies [ICCPCT], pp: 1074 – 1076, 2014.
- Athas,W. C., Svensson, L. J., Koller, G. G., Tzartzanis, N., “Low power Digital System based on Adiabatic Switching Principles”, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. Vol 2, no 4398-407, Dec. 1994.
- Mousam Halder, “Implementation of High Speed Low Power Carry Look Ahead Adder Using Domino Logic” Int. Journal of Applied Sciences and Engineering Research, Vol. 1, No. 3, 2012
- Nayereh Ghobadi, Rabe’eh Majidi, Mahdieh Mehran, and Ali AfzaliKusha, “Low Power 4-Bit Full Adder Cells in Subthreshold Regime” 18th Iranian Conference on Electrical Engineering , pp: 2164-7054, May. 2010
- R.Uma,“ 4-Bit Fast Adder Design: Topology and Layout with SelfResetting Logic for Low Power VLSI Circuits”, International journal of advanced engineering sciences and technologies, Vol No. 7, Issue No. 2, pp:197 – 205, 2011.
- Jan.M Rabaey, Anantha Chandrakasan, Borivoje Nikolic., “Digital Integrated Circuits”, A design perspective, 2nd ed. PHI Learning Private Limited New Delhi, 2011, pp. 559–586.
- Neil H. E Weste, David Harris, Ayan Banerjee “CMOS VLSI Design”, A circuits and systems perspective, 3rd ed., Pearson publications, 2005, pp.111–135.
- Kamran Eshraghian, Douglas A. Pucknell, Sholeh Eshraghian“Essentials of VLSI Circuits and Systems PHI Learning Private Limited New Delhi, 2013, pp. 377–381.
- Sung-Mo Kang, Yusuf Leblebici., “CMOS Digital Integrated circuits”, analysis and Design, 3rd ed., McGraw Hill Education Private Limited, India, 2003, pp.274–317.
Abstract Views: 411
PDF Views: 3