Table of Contents
Vol 9, No 5 (2017)
Open Access
Subscription Access
Articles
A 30nW Sub-Threshold Adiabatic Carry Look-Ahead Adder in 90nm CMOS | ||
S. Saraswathi, G. K. V. N. Sharada | ||
Vol 9, No 5 (2017), Pagination: 85-88 | ||
ABSTRACT | PDF | Abstract Views: 410 | PDF Views: 3 |
Analysis of Floorplanning Techniques for ASIC Development | ||
Sachin Pandya, Rajendrakumar Patel | ||
Vol 9, No 5 (2017), Pagination: 89-95 | ||
ABSTRACT | PDF | Abstract Views: 299 | PDF Views: 4 |
Design & Analysis of an Area-Efficient, Low-Power 8-Bit Multiplier in Modified GDI Cells Using the Urdhva-Tiryagbhyam Theorem | ||
Bobby Nelson, Ravi Tiwari | ||
Vol 9, No 5 (2017), Pagination: 96-103 | ||
ABSTRACT | PDF | Abstract Views: 248 | PDF Views: 2 |
Review of Multi-Bit Flip Flop Technique | ||
Nareshchandra Patel, Mehul L. Patel | ||
Vol 9, No 5 (2017), Pagination: 104-109 | ||
ABSTRACT | PDF | Abstract Views: 257 | PDF Views: 2 |
Design of a Low-Power & Lower-Delay 8-Bit SRAM Cell Using Pulsed Latch Circuit in 32nm Technology | ||
N. Namrata, Khemraj Deshmukh | ||
Vol 9, No 5 (2017), Pagination: 110-115 | ||
ABSTRACT | PDF | Abstract Views: 249 | PDF Views: 4 |