Design & Analysis of an Area-Efficient, Low-Power 8-Bit Multiplier in Modified GDI Cells Using the Urdhva-Tiryagbhyam Theorem

The paper presents the implementation of a low-power and area-efficient 8-bit multiplier using the concepts of ancient Vedic Mathematics, more specifically the Urdhva-Tiryagbhyam theorem. The design of the aforementioned multiplier has been carried out using Modified-Gate-Diffusion-Input cells, which facilitate the reduction of the transistor count while maintaining a full voltage-swing, thereby, consuming even lower power than the CMOS implementation of the Vedic Multiplier.