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Design & Analysis of an Area-Efficient, Low-Power 8-Bit Multiplier in Modified GDI Cells Using the Urdhva-Tiryagbhyam Theorem


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1 Department of Electronics & Telecommunication (VLSI Design), SSTC, Shri Shankaracharya Group of Institutions, Junwani, Bhilai, CG, India
     

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The paper presents the implementation of a low-power and area-efficient 8-bit multiplier using the concepts of ancient Vedic Mathematics, more specifically the Urdhva-Tiryagbhyam theorem. The design of the aforementioned multiplier has been carried out using Modified-Gate-Diffusion-Input cells, which facilitate the reduction of the transistor count while maintaining a full voltage-swing, thereby, consuming even lower power than the CMOS implementation of the Vedic Multiplier.

Keywords

Area-Efficient, CMOS, Gate Diffusion Input, Low-Power, Multiplier, Urdhva-Tiryagbhyam Theorem.
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  • Design & Analysis of an Area-Efficient, Low-Power 8-Bit Multiplier in Modified GDI Cells Using the Urdhva-Tiryagbhyam Theorem

Abstract Views: 252  |  PDF Views: 2

Authors

Bobby Nelson
Department of Electronics & Telecommunication (VLSI Design), SSTC, Shri Shankaracharya Group of Institutions, Junwani, Bhilai, CG, India
Ravi Tiwari
Department of Electronics & Telecommunication (VLSI Design), SSTC, Shri Shankaracharya Group of Institutions, Junwani, Bhilai, CG, India

Abstract


The paper presents the implementation of a low-power and area-efficient 8-bit multiplier using the concepts of ancient Vedic Mathematics, more specifically the Urdhva-Tiryagbhyam theorem. The design of the aforementioned multiplier has been carried out using Modified-Gate-Diffusion-Input cells, which facilitate the reduction of the transistor count while maintaining a full voltage-swing, thereby, consuming even lower power than the CMOS implementation of the Vedic Multiplier.

Keywords


Area-Efficient, CMOS, Gate Diffusion Input, Low-Power, Multiplier, Urdhva-Tiryagbhyam Theorem.

References