| Issue | Title | |
| Vol 8, No 8 (2016) | Grey Wolf Optimizer for Constrained Hardware-Software Codesign Partitioning | Abstract |
| S. Prakasam, Dr. M. Venkatachalam, Dr. M. Saroja | ||
| Vol 5, No 2 (2013) | Grid Connected Wind-Hydro Hybrid System with Battery Energy Storage for Critical Load | Abstract |
| J. Vivekananthan, K. Rajeshkumar | ||
| Vol 2, No 9 (2010) | Hardware Implementation of CRC Architectures | Abstract |
| Jayashree C. Nidagundi, Renuka H. Korti | ||
| Vol 5, No 8 (2013) | Hardware Implementation of Digital Filters For Image De-Noising Applications | Abstract |
| Pooja Dhok, A. D. Jadhav | ||
| Vol 5, No 7 (2013) | Hardware Trojan Rectification and Reducing Trojan Activation Time Using Transition Probability and Dummy Flipflops | Abstract |
| R. Gomathi, A. Jeyasingh | ||
| Vol 3, No 10 (2011) | Hardware-Friendly Vision Algorithm Using FPGA Embedded I/O Resources | Abstract |
| A. Gokulanathan, S. Harikumar | ||
| Vol 5, No 7 (2013) | Harmonic Elimination Using Switching Frequency in H-bridge Cascaded Multilevel Inverter | Abstract |
| P. K. Dhal, C. Christober Asir Rajan | ||
| Vol 7, No 5 (2015) | Harmonic Level Analysis Scenario of Large Scale Process Industry | Abstract |
| K. Balraj, S. Bhuvaneswari | ||
| Vol 9, No 3 (2017) | High - Speed and Low - Power Carry Skip Adder Operated on Wide Range of Supply Voltage Level | Abstract |
| P. Sangeetha, N. Savitha, S. Nithya Devi | ||
| Vol 5, No 8 (2013) | High Efficiency Four Quadrant Operation of Three Phase BLDC Motor with Load Variations | Abstract |
| K. Sakthivel, S. Dhayanandh | ||
| Vol 3, No 8 (2011) | High Performance Electrical & Optical Interconnects | Abstract |
| Jyoti Kedia, Neena Gupta | ||
| Vol 5, No 8 (2013) | High Speed CMOS Differential Logic Design for Carry Lookahead Adder | Abstract |
| Yogeshwaran Kandasamy | ||
| Vol 3, No 13 (2011) | High-Frequency Inverter with Active Regenerative Snubber | Abstract |
| P. Radika, Subhransu Sekhar Dash | ||
| Vol 1, No 7 (2009) | High-Speed 4 BIT Flash ADC Using CMOS Latched Comparator with Current Steering Logic SR Latch | Abstract |
| A. Karthikeyan, V. Srividhya, P. Murugeswari | ||
| Vol 8, No 9 (2016) | Hybrid Active Filter for Power Quality Improvement Using Solar Inverter | Abstract |
| C. Ramya, P.S. Sajana, P. Sunil Joseph | ||
| Vol 4, No 11 (2012) | Hybrid Clamped Multi Level Inverters for Grid Connected Solar Electronics | Abstract |
| R. L. Helen Catherine, S. Nithyapriya | ||
| Vol 8, No 7 (2016) | Hybrid Power Plant | Abstract |
| Snehesh Gope | ||
| Vol 3, No 1 (2011) | Implementation and Analysis of Controlling a Synchronous Motor by Using a Predictive Current Control with the Help of FPGA | Abstract |
| R. Sivaraman, V. Sandeep, K. V. Shriram | ||
| Vol 4, No 5 (2012) | Implementation of 180nm CMOS Linear Feedback Shift Register (LFSR) ASIC for Data Encryption and Decryption | Abstract |
| Fazal Noorbasha, S. Dayasagar Chowdary, K. Hari Kishore, Shaik Moulali | ||
| Vol 4, No 10 (2012) | Implementation of 8-Channel Temperature Scanner Using Programmable System on Chip 3 | Abstract |
| Varun A. Patel, Vrushank A. Patel, Meet H. Patel, Vismit K. Patel, Hardik P. Modi | ||
| Vol 4, No 4 (2012) | Implementation of 90nm Technology Multi Test Pattern Sequence LFSR for Fault Testing | Abstract |
| Fazal Noorbasha, Ch. Hemanth, A. Sivasairam, V. Vijaya Raju | ||
| Vol 2, No 11 (2010) | Implementation of Active Filters for Speech Processing using Switched-Capacitors | Abstract |
| Magesh Kannan Parthasarathy, Mridula Pratap, Gayathri Gopakumar | ||
| Vol 8, No 4 (2016) | Implementation of ALU Using Low Power Full Adder and Multiplexer | Abstract |
| Anitesh Sharma, Ravi Tiwari | ||
| Vol 4, No 7 (2012) | Implementation of Automatic Tuner for Adaptive Hill Climbing MPPT Algorithm | Abstract |
| J. Divya Navamani, A. Lavanya | ||
| Vol 7, No 5 (2015) | Implementation of Body Driven Double Tail Dynamic Comparator for High Speed and Low Power ADC’s | Abstract |
| M. Vaijayanthi, K. Vivek | ||
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