Power Gated Technique to Improve Design Metrics of 6t Sram Memory Cell for Low Power Applications

The SRAM is used in almost every portable device and consumes a considerate amount of device size. Lowering the power dissipation and size of the SRAM memory cell will ultimately lower the average power consumption and size of the digital system. Device scaling is generally used for decreasing the power consumption and the area of the digital system. However, the static power dissipation increases due to device scaling but significant amount of leakage power can be reduced. The low power techniques for SRAM cell implemented in this paper is Power Gating and variations of power gating i.e. using header switch (type 1) and using footer switch (type 2). The purpose of this paper is the application of low power technique in SRAM memory cell to reduce the average power dissipation and simultaneously maintaining the stability of the SRAM memory cells; hence system performance can be improved. The simulation results are carried out using the PTM models for low power on 16nm CMOS technology node using Cadence Virtuoso tool. It can be observed from the result that the power gated SRAM cell exhibits better performance in comparison of conventional 6T SRAM. Depending upon the application, the variations of the power gating technique can be used. The average power dissipated by the power gated SRAM memory cell is 18.07% less than the type 1, whereas it is 15.54% less than type 2. The Write Static Noise Margin (WSNM) of the Power gated SRAM memory cell increases by 3.66% in case of type 1 and 6.17% in case of type 2.