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Triple Material Surrounding Gate MOSFET for Suppression of SCES


Affiliations
1 Department of Electronics and Communication Engineering, Kalyani Government Engineering College, Kalyani-741 235, India
2 Department of Electronics and Tele-Communication Engineering, Jadavpur University, Kolkata-700 032, India
 

Continuous downscaling of conventional MOSFETs suffers from various detrimental shortchannel effects (SCEs). A combination of novel device structures and material property improvement can overcome the SCEs in order to sustain the historical cadence of scaling. In this paper, a comprehensive analysis on the effect of downscaling in the performance of a novel gate-engineered Triple Material (TM) Surrounding Gate (SRG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is presented. With the help of device simulator Silvaco ATLAS, the effect of variation of the radius (R) and the channel length (Lg) on the surface potential, the Electric Field and the drain current is reported in order to provide an enticement for future theoretical studies and experimental researches of the critical aspects of the gate-engineered surrounding gate MOSFET. Results indicate that a trade-off between gate length Lg and channel radius R is necessary to achieve higher immunity against SCEs with a lower OFF-state leakage current to find its usage in ultra low-power applications.

Keywords

Nano-Scale MOSFET, SCEs, TCAD, SRG MOSFET, Triple Material Gate, Gate Engineering.
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  • Triple Material Surrounding Gate MOSFET for Suppression of SCES

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Authors

Angsuman Sarkar
Department of Electronics and Communication Engineering, Kalyani Government Engineering College, Kalyani-741 235, India
Chandan Kr. Sarkar
Department of Electronics and Tele-Communication Engineering, Jadavpur University, Kolkata-700 032, India

Abstract


Continuous downscaling of conventional MOSFETs suffers from various detrimental shortchannel effects (SCEs). A combination of novel device structures and material property improvement can overcome the SCEs in order to sustain the historical cadence of scaling. In this paper, a comprehensive analysis on the effect of downscaling in the performance of a novel gate-engineered Triple Material (TM) Surrounding Gate (SRG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is presented. With the help of device simulator Silvaco ATLAS, the effect of variation of the radius (R) and the channel length (Lg) on the surface potential, the Electric Field and the drain current is reported in order to provide an enticement for future theoretical studies and experimental researches of the critical aspects of the gate-engineered surrounding gate MOSFET. Results indicate that a trade-off between gate length Lg and channel radius R is necessary to achieve higher immunity against SCEs with a lower OFF-state leakage current to find its usage in ultra low-power applications.

Keywords


Nano-Scale MOSFET, SCEs, TCAD, SRG MOSFET, Triple Material Gate, Gate Engineering.

References





DOI: https://doi.org/10.21843/reas%2F2015%2F1-8%2F108322