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An Efficient Viterbi Algorithm for Communication System


Affiliations
1 PG student, Dept of Electronics and Communication, Bharati Vidyapeeth (Deemed to be University) College of Engineering, Pune-43,, India
2 Professor, and Head, Dept of Electronics and Tele-Communication, Bharati Vidyapeeth (Deemed to be University) College of Engineering, Pune-43,, India
     

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The Viterbi decoding algorithm is widely used in areas like Decoding convolutional codes in satellite communication, digital TV, wireless local area networks, mobile relay. Also, the method is used in the development of Automatic Speech Recognition (ASR) and storage systems that work automatically. For Viterbi decoder-based architectures with low latency and complexity, which proposes error detection techniques that are effective. This paper explores the Viterbi algorithm which has two types of approaches for two types of subparts. Important aspects of any communication system are area/power consumption and throughput /efficiency. Minimization of these aspects is the need for an efficient system. This paper explores unwanted logical block reduction by modifying the present logical block. This paper explores signature-based approaches which result in acceptable efficiency. Also, another approach is used to achieve error detection in permanent and transient faults. This error detection is achieved by recomputing with encoded operands. Encoding means the use of shifting operation or the use of rotation operation. This approach makes the system slightly efficient. The proposed approaches can be based on reliability and the efficiency objective.

Keywords

Viterbi Algorithm, Field Programmable Gate Array (FPGA), Transient and Permanent Fault, Self-Checking Adder.
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  • An Efficient Viterbi Algorithm for Communication System

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Authors

Gouri Ganesh Padgal
PG student, Dept of Electronics and Communication, Bharati Vidyapeeth (Deemed to be University) College of Engineering, Pune-43,, India
Shruti Oza
Professor, and Head, Dept of Electronics and Tele-Communication, Bharati Vidyapeeth (Deemed to be University) College of Engineering, Pune-43,, India

Abstract


The Viterbi decoding algorithm is widely used in areas like Decoding convolutional codes in satellite communication, digital TV, wireless local area networks, mobile relay. Also, the method is used in the development of Automatic Speech Recognition (ASR) and storage systems that work automatically. For Viterbi decoder-based architectures with low latency and complexity, which proposes error detection techniques that are effective. This paper explores the Viterbi algorithm which has two types of approaches for two types of subparts. Important aspects of any communication system are area/power consumption and throughput /efficiency. Minimization of these aspects is the need for an efficient system. This paper explores unwanted logical block reduction by modifying the present logical block. This paper explores signature-based approaches which result in acceptable efficiency. Also, another approach is used to achieve error detection in permanent and transient faults. This error detection is achieved by recomputing with encoded operands. Encoding means the use of shifting operation or the use of rotation operation. This approach makes the system slightly efficient. The proposed approaches can be based on reliability and the efficiency objective.

Keywords


Viterbi Algorithm, Field Programmable Gate Array (FPGA), Transient and Permanent Fault, Self-Checking Adder.

References