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An Efficient Viterbi Algorithm for Communication System


Affiliations
1 PG student, Dept of Electronics and Communication, Bharati Vidyapeeth (Deemed to be University) College of Engineering, Pune-43,, India
2 Professor, and Head, Dept of Electronics and Tele-Communication, Bharati Vidyapeeth (Deemed to be University) College of Engineering, Pune-43,, India
     

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The Viterbi decoding algorithm is widely used in areas like Decoding convolutional codes in satellite communication, digital TV, wireless local area networks, mobile relay. Also, the method is used in the development of Automatic Speech Recognition (ASR) and storage systems that work automatically. For Viterbi decoder-based architectures with low latency and complexity, which proposes error detection techniques that are effective. This paper explores the Viterbi algorithm which has two types of approaches for two types of subparts. Important aspects of any communication system are area/power consumption and throughput /efficiency. Minimization of these aspects is the need for an efficient system. This paper explores unwanted logical block reduction by modifying the present logical block. This paper explores signature-based approaches which result in acceptable efficiency. Also, another approach is used to achieve error detection in permanent and transient faults. This error detection is achieved by recomputing with encoded operands. Encoding means the use of shifting operation or the use of rotation operation. This approach makes the system slightly efficient. The proposed approaches can be based on reliability and the efficiency objective.

Keywords

Viterbi Algorithm, Field Programmable Gate Array (FPGA), Transient and Permanent Fault, Self-Checking Adder.
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  • J. Viterbi, “Error bounds for convolutional codes and an asymptotically optimum decoding algorithm,” IEEE Trans. Inf. Theory, vol. 13, no. 2, pp. 260 – 269, 1967.

  • Vaithiyanathana D, Nargisb J, and Seshasayanana R 2015 High-performance ACS for Viterbi decoder using pipeline T-Algorithm, Alexandria Engineering Journal vol 54 issue 3 pp 447–55

  • S. Ranpara and D. S. Ha, “A low-power Viterbi decoder design for wireless communications applications,” IEEE Intl. Conf. Proceedings ASIC/SOC, pp. 377 – 381, Sep.1999.

  • H. Liu, Z. Wang, X. Huang, K. Z. Liu, Z. Wang, X. Huang, and K. Zhang, “High-speed low-power Viterbi decoder design for tcm decoders,” IEEE Trans. VLSI Syst., vol. 20, no. 4, pp. 755–759, Apr 2012.

  • K. Arunlal and S. Hariprasad, “An efficient Viterbi decoder,” Int. Journal of Advanced Information Technology, vol. 2, no. 1, Feb 2012.

  • J. Kong and K. Parhi, “K-nested layered look-ahead method and architectures for high throughput Viterbi decoder,” in Proc. IEEE Workshop on Signal Processing Systems, 2003, pp. 99 – 104.

  • G. Jung, J. Kong, G. Sobelman, and K.Parhi, “High-speed add-compare-select units using locally self-resetting CMOS,” in IEEE Int. Symp.Circuits and Systems, vol. 1, 2002, pp. 889–892.

  • M. Akbar and J.-A. Lee, “Comments on ‘self-checking carry-select adder design based on two-rail encoding’,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 7, pp. 2212–2214, Jul. 2014.

  • Reliable Low-Latency Viterbi Algorithm Architectures Benchmarked on ASIC and FPGA Mehran Mozaffari Kermani, Senior Member, IEEE, Vineeta Singh, Member, IEEE, and Reza Azarderakhsh, Member, IEEE.


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  • An Efficient Viterbi Algorithm for Communication System

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Authors

Gouri Ganesh Padgal
PG student, Dept of Electronics and Communication, Bharati Vidyapeeth (Deemed to be University) College of Engineering, Pune-43,, India
Shruti Oza
Professor, and Head, Dept of Electronics and Tele-Communication, Bharati Vidyapeeth (Deemed to be University) College of Engineering, Pune-43,, India

Abstract


The Viterbi decoding algorithm is widely used in areas like Decoding convolutional codes in satellite communication, digital TV, wireless local area networks, mobile relay. Also, the method is used in the development of Automatic Speech Recognition (ASR) and storage systems that work automatically. For Viterbi decoder-based architectures with low latency and complexity, which proposes error detection techniques that are effective. This paper explores the Viterbi algorithm which has two types of approaches for two types of subparts. Important aspects of any communication system are area/power consumption and throughput /efficiency. Minimization of these aspects is the need for an efficient system. This paper explores unwanted logical block reduction by modifying the present logical block. This paper explores signature-based approaches which result in acceptable efficiency. Also, another approach is used to achieve error detection in permanent and transient faults. This error detection is achieved by recomputing with encoded operands. Encoding means the use of shifting operation or the use of rotation operation. This approach makes the system slightly efficient. The proposed approaches can be based on reliability and the efficiency objective.

Keywords


Viterbi Algorithm, Field Programmable Gate Array (FPGA), Transient and Permanent Fault, Self-Checking Adder.

References