Low Power and High Variation Tolerant 9T-SRAM Cell at 16-nm Technology Node

Objectives: The objective of this paper is to design a threshold voltage (Vt) variation tolerant low leakage low power SRAM cell. Methods/Analysis: The proposed cell has the same architecture as that of read decoupled 7T SRAM cell (RD7T) with an exception of TG instead of access NMOS transistors. This cell is operated in super-threshold region at power supply varying from 0.62V to 0.77V. Findings: Various design metrics of the proposed cell are estimated and compared with RD7T. The proposed cell offers robustness against the process induced variations by providing a 1.1 × narrower spread in read time (TRA) distribution at a cost of 1.23 × penalty in TRA. It also provides 2.06 × narrower spread in read current (IREAD) distribution at the price of 1.13 × penalty in IREAD. It offers 1.42 × lower leakage current and also a 1.06 × lower hold power as compared to that of RD7T. Moreover, it also provides 1.13 × narrower spread in hold power with same read static noise margin (185 mV). Novelty /Improvement: The Monte Carlo based comparative analysis proves that the suggested cell is tolerant to the Vt fluctuations to a great extent.